This is a Divisional of U.S. Application Ser. No.:10/689,032, filed Oct. 21, 2003 now abandoned, the subject matter of which is incorporated herein by reference.
1. Field of the Invention
The present invention relates to a method for fabricating a gate mask of a semiconductor device, and particularly to a method for fabricating a gate mask of a semiconductor device that is configured to form a polysilicon layer or an amorphous silicon layer on a silicon substrate and to be doped into such a layer with an impurity.
2. Description of the Related Art
A semiconductor device that is configured to form a polysilicon layer or an amorphous silicon layer on a silicon substrate and to be doped into such a layer with an impurity has been employed in the prior art. An example of a process for forming such semiconductor devices will be described hereinafter.
Firstly, a gate insulator layer is deposited on a silicon substrate, and a polysilicon layer or an amorphous silicon layer is deposited thereon. The following description will be made hereinafter based on the assumption that the polysilicon layer is employed.
Next, a PMOS section and an NMOS section are formed on the polysilicon layer by the following procedure as an example.
A mask is firstly formed by a photoresist material on the polysilicon layer to cover a region which is not used for the PMOS section, so that a region used for the PMOS section is exposed. Then, such an exposed region, i.e. a region used for the PMOS section, is doped with Group III impurities such as boron by means of ion implantation. The mask is then removed. Accordingly, the PMOS section is formed on the polysilicon layer.
Another mask is then formed by a photoresist material on the polysilicon layer to cover a region which is not used for the NMOS section, so that a region used for the NMOS section is exposed. Then, such an exposed region, i.e. a region used for the NMOS section, is doped with Group V impurities such as phosphorus by means of ion implantation. The mask is then removed in turn. Accordingly, the NMOS section is formed on the polysilicon layer. It should be noted that a forming sequence of the PMOS section and the NMOS section is arbitrarily determined depending on the structure of the semiconductor device.
A heat treatment is then made in order to activate impurity ions which were doped. An oxide film which is formed over the polysilicon layer during the heat treatment is required to be removed.
A tungsten silicide (WSix) layer is then deposited on the polysilicon layer when necessary, thereafter, a nitride layer is deposited thereon.
The nitride layer is then fabricated into an arbitrary pattern. Thereafter, a region of the tungsten silicide layer and the polysilicon layer which is not covered by the nitride layer is removed by etching.
In the aforementioned method, a gate structure of the semiconductor device is formed with an arbitrary pattern.
In the aforementioned fabrication process, the deposition process of the nitride layer is normally carried out at a temperature of 750 deg. C. Because of a subsequent heat treatment for the activation of the source and the drain, some hydrogen atoms which remain in the nitride layer penetrate the tungsten silicide layer, and then diffuse into the polysilicon layer. These hydrogen atoms which have diffused in the polysilicon layer can affect the Group III impurities such as boron which was doped in the polysilicon layer. Specifically, the hydrogen atoms result in a acceleration of the diffusion rate of the Group III impurities. As a result, the Group III impurities may diffuse until they reach the gate insulator layer, and may penetrate the polysilicon layer. For this reason, the threshold voltages Vt vary greatly from device to device when the semiconductor devices are configured to form the polysilicon layer or the amorphous silicon layer which is doped with Group III impurities, in the vicinity of the nitride layer. Consequently, the semiconductor devices pose a reliability problem when the polysilicon layer or the amorphous silicon layer is formed in the vicinity of the nitride layer and doped with Group III impurities. Such a problem is frequently seen in semiconductor devices such as CMOS devices, in particular, in dual gate CMOS devices.
With regard to the fabrication method of the semiconductor devices, a number of techniques to control the amount of hydrogen are disclosed.
For example, a deposition technique using a gas which does not contain hydrogen bond is disclosed (reference is, for example, made to Japanese Patent Laid-open No. 5-29301).
Alternatively, a technique for the deposition of the nitride layer by controlling a flow rate ratio of NH3 to SiH4 and a flow rate ratio of N2 to SiH4 in the range of 2-10 and 13-17, respectively, is disclosed (references are, for example, made to Japanese Patent Laid-open No. 5-29301 and Japanese Patent Laid-open No. 5-171443).
According to the technique disclosed in Japanese Patent Laid-open No. 5-29301, an example which uses a N2 gas for the deposition of the insulator layer (the nitride layer) is described. Such example described in the above patent document, however, poses a problem of low deposition rate in the nitride layer formation, since N2 is hardly decomposed. Moreover, processing of N2 requires not only the use of technologies such as plasma, but also a process condition at an ultra-high temperature that is 800 deg. C. or more. For this reason, it is necessary that the fabrication unit of the semiconductor device satisfies processing conditions requiring a mechanism to generate plasma and maintaining ultra-high temperature. Consequently, the fabrication unit of the semiconductor device according to the technique disclosed in Japanese Patent Laid-open No. 5-29301 pose a problem requiring a complicated fabrication unit.
According to the technique disclosed in Japanese Patent Laid-open No. 5-171443, a nitride silicon layer having fewer dangling bonds is obtained by increasing the amount of hydrogen in the gas phase so as to bind hydrogen atoms with the dangling bonds of silicon atoms and nitrogen atoms. However, according to the disclosed technique in Japanese Patent Laid-open No. 5-171443, the diffusion of hydrogen atoms from the nitride layer into the polysilicon layer or the amorphous silicon layer is not taken into account. In the disclosed technique in Japanese Patent Laid-open No. 5-171443, a diffusion rate of Group III impurities such as boron is, therefore, increased by hydrogen which has diffused in the polysilicon layer or the amorphous silicon layer, thus the impurities may diffuse until they reach the gate insulator layer and may penetrate the polysilicon layer. As a result, the threshold voltages Vt of the semiconductor devices vary greatly from device to device when the polysilicon layer or the amorphous silicon layer is formed in the vicinity of the nitride layer and is doped with Group III impurities. Consequently, the semiconductor devices result in low reliability when the polysilicon layer or the amorphous silicon layer is formed in the vicinity of the nitride layer and is doped with Group III impurities.
3. Object and Advantage of the Invention
Accordingly, it is an object of the present invention to provide a fabrication method of a semiconductor device with improved reliability by reducing the amount of hydrogen atoms remaining in the nitride layer so that each threshold voltage Vt of the fabricated semiconductor device does not deviate with respect to each device, wherein the semiconductor devices are configured to form the polysilicon layer or the amorphous silicon layer, which is doped with Group III impurities, in the vicinity of the nitride layer.
4. Summary of the Invention
In order to solve the aforementioned problems, a method for fabricating a gate mask of a semiconductor device according to one feature of the present invention is characterized in that a nitride layer of the gate mask for the semiconductor device is deposited at a temperature over 750 deg. C. so as to release hydrogen from the nitride layer. Accordingly, hydrogen can be released from the nitride layer, thereby the amount of hydrogen atoms remaining in the nitride layer can be reduced.
A method for fabricating a gate mask of a semiconductor device according to another feature of the present invention is characterized in that a nitride layer of the gate mask for the semiconductor device is deposited in a gas atmosphere of an ammonia gas and a silane gas such that a flow rate of the ammonia gas is set at twenty times or more than the flow rate of the silane gas. That is, a nitride layer is deposited by using a feed gas which contains less hydrogen, thereby the amount of hydrogen atoms remaining in the nitride layer can be reduced.